IBM Unveils World's First Sub-1nm Chip With Nanostack Technology

A radical new 3D transistor architecture packs nearly 100 billion transistors onto a fingernail-sized chip, pointing toward the next decade of computing.

IBM's new chip architecture pushes transistor density to nearly 100 billion per fingernail-sized die.

IBM has reportedly broken through one of semiconductor manufacturing's most stubborn physical barriers. On June 25, the company unveiled what it calls the world's first sub-1 nanometer chip technology, built on a node measuring just 0.7 nanometers, or 7 angstroms. The breakthrough doesn't just shrink transistors further; it rethinks how they're built in the first place.

A New Architecture Called Nanostack

Rather than continuing to shrink transistors across a flat, two-dimensional plane, IBM researchers developed what they're calling "Nanostack," an evolution of the nanosheet (gate-all-around) design used in today's leading-edge chips. According to IBM, Nanostack uses 3D sequential integration to vertically stack and stagger two layers of transistors, bonding them together with an ultra-thin dielectric. This structural shift, rather than further atomic-level shrinking, is reportedly what allowed engineers to bypass the physical limitations that have slowed progress at the bleeding edge of chipmaking.

Nearly 100 Billion Transistors on a Fingernail

The numbers behind the prototype are striking. IBM says the new chip crams close to 100 billion transistors onto a piece of silicon roughly the size of a fingernail, nearly double the density of the company's previous 2-nanometer benchmark unveiled back in 2021. Compared with that 2nm predecessor, IBM claims the new design can deliver up to 50% higher performance or, alternatively, up to 70% greater energy efficiency, depending on how a chipmaker chooses to tune it. Researchers also reported a 40% improvement in SRAM scaling, which could let designers build much denser, more efficient on-chip memory for data-hungry AI workloads.

Vertical 3D stacking, rather than further flat shrinking, is the structural basis of IBM's Nanostack design.

Why This Matters for AI and Data Centers

The timing is notable. AI infrastructure spending has been consuming capital at an extraordinary scale this year, with hyperscalers and chipmakers alike racing to squeeze more performance per watt out of every data center rack. A chip architecture that reportedly offers a meaningful jump in either raw performance or energy efficiency, IBM's own framing, could matter enormously for AI training and inference clusters straining against power constraints. Sources close to the project suggest the SRAM density gains in particular could ease bottlenecks in memory-bound AI accelerators, a pain point that has shaped chip design conversations throughout 2026.

A Demonstration, Not a Product Yet

IBM has been careful to frame Nanostack as a technology demonstration rather than something heading to market imminently. The company says it has not yet disclosed how, or with which partners, it plans to commercialize the architecture, and its near-term focus remains helping foundry partners scale today's 2nm nanosheet process into volume production. That caveat carries weight: IBM's 2nm chip, first revealed in 2021, is only now approaching mass-market manufacturing five years later. If history is any guide, sub-1nm Nanostack chips reaching consumer devices or data centers could still be the better part of a decade away.

Commercialization of sub-1nm chips is reportedly still years away, with 2nm production only now ramping up.

The Bigger Picture for Chipmaking

Nanostack arrives amid a broader industry pivot toward 3D and vertically integrated chip designs, as traditional two-dimensional scaling approaches the limits described by Moore's Law. Competing approaches from other major foundries are reportedly exploring similar stacked-transistor concepts, suggesting the industry is converging on vertical integration as the next major lever for performance gains. For now, IBM's announcement serves as a proof of concept that the angstrom-era roadmap, once considered close to physically impossible, still has room to run.

Vertical transistor stacking may define the next decade of processor design across the industry.